ERROR:Xst:827 = Signal count cannot be synthesized, bad synchronous description

Your code seems very mixed up. There is a specific reason why it won’t synthesise: think carefully when the code immediately following this line here

elsif (updownpassenger="1") then

will be executed. It will be executed following a positive edge or negative edge on any input in the sensitivity list, apart from clk where it will be executed only following a negative edge. How would you design logic with such behaviour? Well, your synthesiser can’t do it, either.

Basically, you need to refactor your code. You need to split it into sequential and combinational processes. (Combinational logic is logic whose output depends only on it’s input and thus is logic that contains no latches or flip-flops. Sequential logic is logic that contains latches or flip-flops, but will also usually contain some gates too. Do not use latches – they are not synchronous design.) Whilst there are many ways to code such processes, it is wise to be consistent by sticking to a template. Here are three templates, which if followed, will give you everything you need and will keep your VHDL coding life simple:

Here is the template for sequential logic with an asynchronous reset, which all synthesis tools should understand:

process(clock, async_reset)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if async_reset="1" then  -- or '0' for an active low reset
        -- set/reset the flip-flops here
        -- ie drive the signals to their initial values
    elsif rising_edge(clock) then  -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;        

Here is the template for sequential logic without an asynchronous reset:

process(clock)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if rising_edge(clock) then  -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;        

And here is the corresponding template for a combinational process:

process(all inputs in the sensitivity list)  -- an 'input' is a signal either on the LHS of an assignment or a signal that is tested
begin
     -- combinational logic (with complete assignment and no feedback)
end process;