Another solution that’s been proposed for this is POST Once Exactly (POE), in which the server generates single-use POST URIs that, when used more than once, will cause the server to return a 405 response. The downsides are that 1) the POE draft was allowed to expire without any further progress on standardization, and thus … Read more
The main difference between AtomicBoolean and volatile from a practical point of view is that the compare-and-set operation isn’t atomic with volatile variables. volatile boolean b; void foo() { if( b ) { //Here another thread might have already changed the value of b to false b = false; } } But seeing as all … Read more
It sounds like the atomic operations on memory will be executed directly on memory (RAM). Nope, as long as every possible observer in the system sees the operation as atomic, the operation can involve cache only. Satisfying this requirement is much more difficult for atomic read-modify-write operations (like lock add [mem], eax, especially with an … Read more
The C++11 memory ordering parameters for atomic operations specify constraints on the ordering. If you do a store with std::memory_order_release, and a load from another thread reads the value with std::memory_order_acquire then subsequent read operations from the second thread will see any values stored to any memory location by the first thread that were prior … Read more
This is the likely implementation for Interlocked.Exchange() in the CLR, copied from the SSCLI20 source: Note that UP in the function name means UniProcessor. This is not atomic on SMP / multi-core systems. This implementation will only be used by CLR on single-core systems. FASTCALL_FUNC ExchangeUP,8 _ASSERT_ALIGNED_4_X86 ecx mov eax, [ecx] ; attempted comparand retry: … Read more
No, you don’t need barriers, but your code is broken anyway if readers and writers call these functions in different threads. Especially if a reader calls the read function in a loop. TL:DR: use C++11 std::atomic<long> m_value with return m_value++ in the increment and return m_value in the reader. That will give you sequential consistency … Read more
Yes all “normal” ISAs including 8080 and x86 guarantee that instructions are atomic with respect to interrupts on the same core. Either an instruction has fully executed and all its architectural effects are visible (in the interrupt handler), or none of them are. Any deviations from this rule are generally carefully documented. For example, Intel’s … Read more
Make me think of a sequence lock. Not very accurate (putting this from memory) but something along the lines of: let x,y and s be 64 bit integers. To increment: atomic s++ (I mean atomic increment using 64 bit CAS op) memory barrier atomic x++ atomic y++ atomic s++ memory barrier To read: do { … Read more
The answer depends on your definition of “atomic” I know of three valid definitions for atomic: Atomic as in synchronized: only one thread can be executing the code at one time; Atomic as in ACID: all of the action/block happens, or none of it does; Atomic as in uninterruptible: once the block starts, it can’t … Read more
Why would it be? The processor core still needs to read the value stored at the memory location, calculate the increment of it, and then store it back. There’s a latency between reading and storing, and in the mean time another operation could have affected that memory location. Even with out-of-order execution, processor cores are … Read more