instructions

Out-of-order instruction execution: is commit order preserved?

TL:DR: memory ordering is not the same thing as out of order execution. It happens even on in-order pipelined CPUs. In-order commit is necessary1 for precise exceptions that can roll-back to exactly the instruction that faulted, without any instructions after that having already retired. The cardinal rule of out-of-order execution is don’t break single-threaded code. … Read more

What are the semantics of ADRP and ADRL instructions in ARM assembly?

ADR ADR is a simple PC-relative address calculation: you give it an immediate offset, and it stores in the register the address relative to the current PC. For example, if the following ADR instruction is placed at position 0x4000 in memory: adr x0, #1 then after this instruction is executed x0 now contains the value … Read more

How does x86 pause instruction work in spinlock *and* can it be used in other scenarios?

PAUSE notifies the CPU that this is a spinlock wait loop so memory and cache accesses may be optimized. See also pause instruction in x86 for some more details about avoiding the memory-order mis-speculation when leaving the spin-loop. PAUSE may actually stop CPU for some time to save power. Older CPUs decode it as REP … Read more

Which arithmetic operations are the same on unsigned and two’s complement signed numbers?

Addition, subtraction and multiplication are the same provided: Your inputs and outputs are the same size Your behaviour on overflow is wraparound modulo 2n Division is different. Many instruction sets offer multiplication operations where the output is larger than the input, again these are different for signed and unsigned. Furthermore if you are writing your … Read more