There are very good reasons to have a fixed instruction length, implementation simplicity being the most important. That’s why many processors do indeed have a fixed instruction length, like RISC processors and many early computers. CISC instruction sets like x86 are desinged to be decoded sequentially (step by step) by microcode. (you can think of … Read more
Straight from Intel, here’s an explanation of how recent processors maintain a TSC that ticks at a constant rate, is synchronous between cores and packages on a multi-socket motherboard, and may even continue ticking when the processor goes into a deep sleep C-state, in particular see the explanation by Vipin Kumar E K (Intel): http://software.intel.com/en-us/articles/best-timing-function-for-measuring-ipp-api-timing/ … Read more
ARM calls FIQ the fast interrupt, with the implication that IRQ is normal priority. In any real system, there will be many more sources of interrupts than just two devices and there will therefore be some external hardware interrupt controller which allows masking, prioritization etc. of these multiple sources and which drives the interrupt request … Read more