Difference between x86, x32, and x64 architectures?

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Answer recommended by Intel

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  1. The most correct way to refer to 32-bit and 64-bit versions of programs for x86-related CPUs?
  2. Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
  3. how are barriers/fences and acquire, release semantics implemented microarchitecturally?
  4. What specifically marks an x86 cache line as dirty – any write, or is an explicit change required?
  5. What happens if you use the 32-bit int 0x80 Linux ABI in 64-bit code?
  6. Why doesn’t GCC use partial registers?
  7. Which cache mapping technique is used in intel core i7 processor?
  8. How can I determine if a .NET assembly was built for x86 or x64?
  9. Globally Invisible load instructions
  10. Why does this function push RAX to the stack as the first operation?
  11. What exactly happens when a skylake CPU mispredicts a branch?
  12. What do the E and R prefixes stand for in the names of Intel 32-bit and 64-bit registers?
  13. Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
  14. If I don’t use fences, how long could it take a core to see another core’s writes?
  15. x86 registers: MBR/MDR and instruction registers
  16. Is LFENCE serializing on AMD processors?
  17. System.BadImageFormatException: Could not load file or assembly (from installutil.exe)
  18. Why is x86 little endian?
  19. Where is the Write-Combining Buffer located? x86
  20. x86_64 ASM – maximum bytes for an instruction?
  21. What kind of address instruction does the x86 cpu have?
  22. What are the costs of failed store-to-load forwarding on x86?
  23. What is the difference between Trap and Interrupt?
  24. Branch target prediction in conjunction with branch prediction?
  25. x86 32 bit opcodes that differ in x86-x64 or entirely removed
  26. How do the store buffer and Line Fill Buffer interact with each other?
  27. Are load ops deallocated from the RS when they dispatch, complete or some other time?
  28. Why did Intel change the static branch prediction mechanism over these years?
  29. Are two store buffer entries needed for split line/page stores on recent Intel?
  30. What is the maximum possible IPC can be achieved by Intel Nehalem Microarchitecture?

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