how does push and pop work in assembly
The latter POP EBP is equivalent to MOV EBP, [ESP] ADD ESP, 4 ; but without modifying flags, like LEA ESP, [ESP+4] (in Intel syntax – target on the left, source on the right)
The latter POP EBP is equivalent to MOV EBP, [ESP] ADD ESP, 4 ; but without modifying flags, like LEA ESP, [ESP+4] (in Intel syntax – target on the left, source on the right)
Carry flag is carry or borrow out of the Most Significant bit (MSb): CF (bit 0) Carry flag — Set if an arithmetic operation generates a carry or a borrow out of the mostsignificant bit of the result; cleared otherwise. This flag indicates an overflow condition for unsigned-integer arithmetic. It is also used in multiple-precision … Read more
Right-click the project, not the solution. Then Build Dependencies + Build Customizations. You get the dialog, tick “masm”.
In 64-bit mode you cannot push and pop 32-bit values; you need pushq and popq. Also, you will not get a proper exit this way. On 32-bit x86, you would need to set %eax to 1 to select the exit() system call, and set %ebx to the exit code you actually wish. On 64-bit x86 … Read more
See Why Does GCC LEA EIZ?: Apparently %eiz is a pseudo-register that just evaluates to zero at all times (like r0 on MIPS). … I eventually found a mailing list post by binutils guru Ian Lance Taylor that reveals the answer. Sometimes GCC inserts NOP instructions into the code stream to ensure proper alignment and … Read more
try break *0x0000000000400448
I think I’d use pointers into the current position into the list, instead of an index that needs to be scaled every time you use it: mov esi, offset list top: mov edi, esi inner: mov eax, [edi] mov edx, [edi+4] cmp eax, edx jle no_swap mov [edi+4], eax mov [edi], edx no_swap: add edi, … Read more
You can put the argv array onto the stack and load the address of it into rsi. The first member of argv is a pointer to the program name, so we can use the same address that we load into rdi. xor edx, edx ; Load NULL to be used both as the third ; … Read more
You’re right, a modern x86 will decode add dword [mem], 1 to 3 uops: a load, an ALU add, and a store. (This is actually a simplification of various things, including Intel’s micro-fusion and how AMD always keeps a load+ALU together in some parts of the pipeline…) Those 3 dependent operations can’t happen at the … Read more
First, a paper you should consider reading, if you want to understand floating point foibles better: “What Every Computer Scientist Should Know About Floating Point Arithmetic,” http://www.validlab.com/goldberg/paper.pdf And now to some meat. The following code is bare bones, and attempts to produce an IEEE-754 single precision float from an unsigned int in the range 0 … Read more