Verilog generate/genvar in an always block
You need to reverse the nesting inside the generate block: genvar c; generate for (c = 0; c < ROWBITS; c = c + 1) begin: test always @(posedge sysclk) begin temp[c] <= 1’b0; end end endgenerate Technically, this generates four always blocks: always @(posedge sysclk) temp[0] <= 1’b0; always @(posedge sysclk) temp[1] <= 1’b0; … Read more