sequential execution in process statement in vhdl
Constructing a Minimal, Complete, and Verifiable example containing your process: library ieee; use ieee.std_logic_1164.all; entity sequent_exec is end entity; architecture foo of sequent_exec is signal a: std_ulogic := ‘1’; signal b, c: std_ulogic := ‘0’; signal clk: std_ulogic := ‘0’; begin CLOCK: process begin wait for 10 ns; clk <= not clk; if now > … Read more