sequential execution in process statement in vhdl

Constructing a Minimal, Complete, and Verifiable example containing your process: library ieee; use ieee.std_logic_1164.all; entity sequent_exec is end entity; architecture foo of sequent_exec is signal a: std_ulogic := ‘1’; signal b, c: std_ulogic := ‘0’; signal clk: std_ulogic := ‘0’; begin CLOCK: process begin wait for 10 ns; clk <= not clk; if now > … Read more

How to count pressed keys on FPGA spartan board

The effect you are witnessing is called “bouncing” of the switch. You need to “debounce” the external input. How to synchronize an external input An external input is not synchronous to the internal clock domain. Thus signal edges within the setup or hold time of a register could cause metastability. You need to synchronize your … Read more

shift a std_logic_vector of n bit to right or left

Use the ieee.numeric_std library, and the appropriate vector type for the numbers you are working on (unsigned or signed). Then the operators are `sla`/`sra` for arithmetic shifts (ie fill with sign bit on right shifts and lsb on left shifts) and `sll`/`srl` for logical shifts (ie fill with ‘0’s). You pass a parameter to the … Read more