It depends on how you address the data. If you use 32 bits to address each bit, you can address 232 bits or 4Gb = 512MB. If you address bytes like most current architectures it will give you 4GB. But if you address much larger blocks you will need less bits to address 4GB. For … Read more
The Motorola 88100 had a single register file (thirty-one 32-bit entries plus a hardwired zero register) used for floating point and integer values. With 32-bit registers and support for double precision, register pairs had to be used to supply values, significantly constraining the number of double precision values that could be kept in registers. The … Read more
A summary and additional discussion can be found at: L1 caches usually have split design, but L2, L3 caches have unified design, why?. Introduction A split cache is a cache that consists of two physically separate parts, where one part, called the instruction cache, is dedicated for holding instructions and the other, called the data … Read more
Speculative execution and out-of-order execution are orthogonal. One could design a processor that is OoO but not speculative or speculative but in-order. OoO execution is an execution model in which instructions can be dispatched to execution units in an order that is potentially different from the program order. However, the instructions are still retired in … Read more