What is the maximum possible IPC can be achieved by Intel Nehalem Microarchitecture?
TL:DR: Intel Core, Nehalem, and Sandybridge / IvyBridge: a maximum of 5 IPC, including 1 macro-fused cmp+branch to get 5 instructions into 4 fused-domain uops, and the rest being single-uop instruction. (up to 2 of these can be micro-fused store or load+ALU.) Haswell up to 9th Gens: a maximum of 6 instructions per cycle can … Read more