How does signal assignment work in a process?

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Variables get updated as you assign them. Signals get update in the next delta cycle (at the earliest). 

a := '1'; -- variable
assert a = 1;
b <= '1'; -- signal
computationUsing(b); --reads old value of b
-- new value will be visible after this process ends or some time passes

Jan Decaluwe explains this stuff in more detail here: http://www.sigasi.com/content/vhdls-crown-jewel

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