Is there a simple example of how to generate verilog from Chisel3 module?
Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project. scalaVersion := “2.13.8” addCompilerPlugin(“edu.berkeley.cs” % “chisel3-plugin” % “3.5.3” … Read more