Is there a simple example of how to generate verilog from Chisel3 module?

Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template

If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project.

scalaVersion := "2.13.8"

addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.3"

Put the above GCD source code in GCD.scala and add the following to the file:

import chisel3.stage.ChiselStage

object GCDDriver extends App {
  (new ChiselStage).emitVerilog(new GCD, args)
}

You can then generate the Verilog by running: sbt "runMain GCDDriver". The default output directory is the current directory.

You can see what command-line options are available by running sbt "runMain GCDDriver --help" For example --target-dir will let you change the target directory