memory-model
Is Dalvik’s memory model the same as Java’s?
As of 4.0 (Ice Cream Sandwich), Dalvik’s behavior should match up with JSR-133 (the Java Memory Model). As of 3.0 (Honeycomb), most of the pieces were in place, but some minor things had been overlooked that would be difficult to encounter in practice (e.g. some edge cases in finalization). As of 2.3 (Gingerbread), Dalvik was … Read more
C++ memory model and race conditions on char arrays
I think Bjarne is wrong about this, or at least, he’s simplifying things considerably. Most modern processors are capable of writing a byte without reading a complete word first, or rather, they behave “as if” this were the case. In particular, if you have a char array[2];, and thread one only accesses array[0] and thread … Read more
What do each memory_order mean?
The GCC Wiki gives a very thorough and easy to understand explanation with code examples. (excerpt edited, and emphasis added) IMPORTANT: Upon re-reading the below quote copied from the GCC Wiki in the process of adding my own wording to the answer, I noticed that the quote is actually wrong. They got acquire and consume … Read more
Does Interlocked.CompareExchange use a memory barrier?
Any x86 instruction that has lock prefix has full memory barrier. As shown Abel’s answer, Interlocked* APIs and CompareExchanges use lock-prefixed instruction such as lock cmpxchg. So, it implies memory fence. Yes, Interlocked.CompareExchange uses a memory barrier. Why? Because x86 processors did so. From Intel’s Volume 3A: System Programming Guide Part 1, Section 7.1.2.2: For … Read more
How to understand happens-before consistent
Each thread can be on a different core with its own private registers which Java can use to hold values of variables, unless you force access to coherent shared memory. This means that one thread can write to a value storing in a register, and this value is not visible to another thread for some … Read more
Will two atomic writes to different locations in different threads always be seen in the same order by other threads?
This kind of reordering test is called IRIW (Independent Readers, Independent Writers), where we’re checking if two readers can see the same pair of stores appear in different orders. Related, maybe a duplicate: Acquire/release semantics with 4 threads The very weak C++11 memory model does not require that all threads agree on a global order … Read more
C++11 introduced a standardized memory model. What does it mean? And how is it going to affect C++ programming?
First, you have to learn to think like a Language Lawyer. The C++ specification does not make reference to any particular compiler, operating system, or CPU. It makes reference to an abstract machine that is a generalization of actual systems. In the Language Lawyer world, the job of the programmer is to write code for … Read more