Is there any architecture that uses the same register space for scalar integer and floating point operations?

by

The Motorola 88100 had a single register file (thirty-one 32-bit entries plus a hardwired zero register) used for floating point and integer values. With 32-bit registers and support for double precision, register pairs had to be used to supply values, significantly constraining the number of double precision values that could be kept in registers.

The follow-on 88110 added thirty-two 80-bit extended registers for additional (and larger) floating point values.

Mitch Alsup, who was involved in Motorola’s 88k development, has developed his own load-store ISA (at least partially for didactic reasons) which, if I recall correctly, uses a unified register file.

It should also be noted that the Power ISA (descendant from PowerPC) defines an “Embedded Floating Point Facility” which uses GPRs for floating point values. This reduces core implementation cost and context switch overhead.

One benefit of separate register files is that such provides explicit banking to reduce register port count in a straightforward limited superscalar design (e.g., providing three read ports to each file would allow all pairs of one FP, even three-source-operand FMADD, and one GPR-based operation to start in parallel and many common pairs of GPR-based operations compared with a five read ports with single register file to support FMADD and one other two-source operation). Another factor is that the capacity is additional and the width independent; this has both advantages and disadvantages. In addition, by coupling storage with operations a highly distinct coprocessor can be implemented in a more straightforward manner. This was more significant for early microprocessors given chip size limits, but the UltraSPARC T1 shared a floating point unit with eight cores and AMD’s Bulldozer shared an FP/SIMD unit with two integer “cores”.

A unified register file has some calling convention advantages; values can be passed in the same registers regardless of the type of the values. A unified register file also reduces unusable resources by allowing all registers to be used for all operations.

More Related Contents:

  1. What is the “FS”/”GS” register intended for?
  2. x86 registers: MBR/MDR and instruction registers
  3. Out-of-order execution vs. speculative execution
  4. Why isn’t the instruction pointer a normal register usable with MOV or ADD?
  5. What does a ‘Split’ cache means. And how is it useful(if it is)?
  6. How does 32-bit address 4GB if 2³² bits = 4 Billion bits not Bytes?
  7. Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register?
  8. Can x86’s MOV really be “free”? Why can’t I reproduce this at all?
  9. What is the purpose of the “Prefer 32-bit” setting in Visual Studio and how does it actually work?
  10. How are x86 uops scheduled, exactly?
  11. What exactly happens when a skylake CPU mispredicts a branch?
  12. Trying to understand gcc option -fomit-frame-pointer
  13. Why is a conditional move not vulnerable to Branch Prediction Failure?
  14. Why can’t you set the instruction pointer directly?
  15. Undefined symbols for architecture x86_64 on Xcode 6.1
  16. CPU and Data alignment
  17. How has CPU architecture evolution affected virtual function call performance?
  18. How does an assembly instruction turn into voltage changes on the CPU?
  19. How does the CPU do subtraction?
  20. How to determine if the registers are loaded right to left or vice versa
  21. x86 Calculating AX given AH and AL?
  22. Latency bounds and throughput bounds for processors for operations that must occur in sequence
  23. Instruction decoding when instructions are length-variable
  24. Can a hyper-threaded processor core execute two threads at the exact same time?
  25. Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
  26. What is the purpose of segment registers in x86 protected mode?
  27. Why can I access lower dword/word/byte in a register but not higher?
  28. What’s the best way to remember the x86-64 System V arg register order?
  29. What specifically marks an x86 cache line as dirty – any write, or is an explicit change required?
  30. Is processor can do memory and arithmetic operation at the same time?

Leave a Comment