They control the behaviour of make for the tagged command lines: @ suppresses the normal ‘echo’ of the command that is executed. – means ignore the exit status of the command that is executed (normally, a non-zero exit status would stop that part of the build). + means ‘execute this command under make -n‘ (or … Read more
Newer versions of GCC have an -MP option which can be used with -MD. I simply added -MP and -MD to the CPPFLAGS variable for my project (I did not write a custom recipe for compiling C++) and added an “-include $(SRC:.cpp=.d)” line. Using -MD and -MP gives a dependency file which includes both the … Read more
In your example, the TMP variable is set (and the temporary directory created) whenever the rules for out.tar are evaluated. In order to create the directory only when out.tar is actually fired, you need to move the directory creation down into the steps: out.tar : $(eval TMP := $(shell mktemp -d)) @echo hi $(TMP)/hi.txt tar … Read more
I would try something along these lines FLAC_FILES = $(shell find flac/ -type f -name ‘*.flac’) MP3_FILES = $(patsubst flac/%.flac, mp3/%.mp3, $(FLAC_FILES)) .PHONY: all all: $(MP3_FILES) mp3/%.mp3: flac/%.flac @mkdir -p “$(@D)” @echo convert “$<” to “$@” A couple of quick notes for make beginners: The @ in front of the commands prevents make from printing … Read more
Lazy Set VARIABLE = value Normal setting of a variable, but any other variables mentioned with the value field are recursively expanded with their value at the point at which the variable is used, not the one it had when it was declared Immediate Set VARIABLE := value Setting of a variable with simple expansion … Read more
There are many good answers here already, but I wanted to share a more complete example that both: doesn’t assume uname exists on Windows also detects the processor The CCFLAGS defined here aren’t necessarily recommended or ideal; they’re just what the project to which I was adding OS/CPU auto-detection happened to be using. ifeq ($(OS),Windows_NT) … Read more
You have several options to set up variables from outside your makefile: From environment – each environment variable is transformed into a makefile variable with the same name and value. You may also want to set -e option (aka –environments-override) on, and your environment variables will override assignments made into makefile (unless these assignments themselves … Read more
Maybe something like # your Makefile #### variables RM= rm -vf CXX= g++ CXXFLAGS= -Wall -g CPPFLAGS= -I/usr/include/opencv -I/usr/include/opencv2 LDLIBS= -lopencv_core -lopencv_imgproc -lopencv_highgui \ -lopencv_ml -lopencv_video -lopencv_features2d \ -lopencv_calib3d -lopencv_objdetect -lopencv_contrib \ -lopencv_legacy -lv4l1 -lv4l2 -lv4lconvert SOURCEFILES= sourc1.cpp sourc2.cpp sourc3.cpp OBJECTFILES= $(patsubst %.cpp,%.o,$(SOURCEFILES)) PROGNAME= yourexe ### rules .PHONY: all clean all: $(PROGNAME) $(PROGNAME): $(OBJECTFILES) $(LINK.cpp) … Read more
As indicated in the online manual, the most common cause for that error is that lines are indented with spaces when make expects tab characters. Correct target: \tcmd where \t is TAB (U+0009) Wrong target: ….cmd where each . represents a SPACE (U+0020).
By default, Makefile targets are “file targets” – they are used to build files from other files. Make assumes its target is a file, and this makes writing Makefiles relatively easy: foo: bar create_one_from_the_other foo bar However, sometimes you want your Makefile to run commands that do not represent physical files in the file system. … Read more