TrustZone monitor mode and IFAR, IFSR, DFAR, DFSR

by

It is worth noting that only external aborts can be configured to be taken in monitor mode, so MMU access faults will not be trapped.

As for the main question: the state of all Secure/Non-secure banked registers while in monitor mode is controlled by the state of the cp15 Secure Configuration Register NS bit: when it is set, you access Non-secure versions, and when it is clear you access Secure versions.

The following is some inline gcc code which allows any secure world mode to inspect these CP15 registers.

    #define MODE_MONITOR 0x16
    unsigned int mode;
    unsigned int world;
    unsigned int dfar;
    unsigned int dfsr;
    unsigned int ifar;
    unsigned int ifsr;

    asm (" mrs %0, cpsr\n"                 /* Save mode. */
         " mrc p15, 0, %1, c1, c1, 0\n"
         " orr  %1, %1, #1\n"              /* Set NS bit in SCR. */
         " cpsid aif, %6\n"                /* To monitor mode... */
         " mcr p15, 0, %1, c1, c1, 0\n"
         " mrc p15, 0, %2, c6, c0, 0\n"
         " mrc p15, 0, %3, c5, c0, 0\n"
         " mrc p15, 0, %4, c6, c0, 2\n"
         " mrc p15, 0, %5, c5, c0, 1\n"
         " bic  %1, %1, #1\n"              /* Clear NS bit in SCR. */
         " mcr  p15, 0, %1, c1, c1, 0\n"
         " isb\n"
         " msr cpsr, %0\n"
         : "=&r" (mode), "=&r" (world),
           "=r"(dfar), "=r"(dfsr),
           "=r"(ifar), "=r"(ifsr)
         : "I" (MODE_MONITOR));
    printf("DFAR: %.8x dfsr: %.8x IFAR: %.8x ifsr: %.8x\n",
           dfar, dfsr, ifar, ifsr);

More Related Contents:

  1. How is load->store reordering possible with in-order commit?
  2. What is the difference between FIQ and IRQ interrupt system?
  3. Arm Neon Intrinsics vs hand assembly
  4. Explaination of ARM (especifically mobile) Peripherals Addressing and Bus architecture?
  5. Explicitly accessing banked registers on ARM
  6. what is the right way to update MMU translation table
  7. SSE _mm_movemask_epi8 equivalent method for ARM NEON
  8. qemu-system-aarch64 entering el1 when emulating a53 power up
  9. Why unsigned types are more efficient in arm cpu?
  10. How to run code from RAM on ARM architecture
  11. Handling ARM TrustZones
  12. How to measure program execution time in ARM Cortex-A8 processor?
  13. Methods to vectorise histogram in SIMD?
  14. exit.c:(.text+0x18): undefined reference to `_exit’ when using arm-none-eabi-gcc
  15. Why use LDR over MOV (or vice versa) in ARM assembly?
  16. How to create static linked shared libraries
  17. How to single step ARM assembly in GDB on QEMU?
  18. Does hardware memory barrier make visibility of atomic operations faster in addition to providing necessary guarantees?
  19. Do Kernel pages get swapped out?
  20. Which variable types/sizes are atomic on STM32 microcontrollers?
  21. How can I do memory test on Arm architecture hardware? (something like Memtest86) [closed]
  22. ARM inline asm: exit system call with value read from memory
  23. Cross compiling static C hello world for Android using arm-linux-gnueabi-gcc
  24. How to work with external libraries when cross compiling?
  25. Android emulator system images and AMD processor
  26. STM32 how to get last reset status
  27. Initial state of program registers and stack on Linux ARM
  28. How to specify an individual register as constraint in ARM GCC inline assembly?
  29. Cross Compile OpenSSH for ARM
  30. Converting Int to Float or Float to Int using Bitwise operations (software floating point)

Leave a Comment