Add $t2 $t3 + $t4 $t5, result in $t0 $t1
addu $t1, $t3, $t5 # add least significant word
sltu $t0, $t1, $t5 # set carry-in bit
addu $t0, $t0, $t2 # add in first most significant word
addu $t0, $t0, $t4 # add in second most significant word
For the second part of your question, there is no status register. None at all. Nada.