What is the compatible subset of Intel’s and AMD’s x86-64 implementations?

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History note: Intel implemented their 64-bit ISA, which they called IA-64 which was a complete replacement of the 32-bit x86 ISA, in their Itanium line of processors. IA-64 wasn’t backward compatible with x86 and never really became popular outside the high-end server market.

AMD created the AMD64 ISA as an incremental evolution over the x86 ISA. AMD64 gained popularity and acceptance quickly and Intel adopted it as well, but called it IA-32e, EM64T and Intel64 at various times. Intel64 and AMD64 are nearly identical with a few differences.

Wikipedia lists these differences:

  • Intel 64’s BSF and BSR instructions act differently than AMD64’s when the source is zero and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.

  • AMD64 requires a different microcode update format and control MSRs (model-specific registers) while Intel 64 implements microcode update unchanged from their 32-bit only processors.

  • Intel 64 lacks some MSRs that are considered architectural in AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.

  • Intel 64 allows SYSCALL/SYSRET only in 64-bit mode (not in compatibility mode), and allows SYSENTER/SYSEXIT in both modes. AMD64 lacks SYSENTER/SYSEXIT in both sub-modes of long mode.

  • In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently. Intel 64 ignores this prefix: the instruction has 32-bit sign extended offset, and instruction pointer is not truncated. AMD64 uses 16-bit offset field in the instruction, and clears the top 48 bits of instruction pointer.

  • AMD processors raise a floating point Invalid Exception when performing an FLD or FSTP of an 80-bit signalling NaN, while Intel processors do not.

  • Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).

  • Recent AMD64 processors have reintroduced limited support for segmentation, via the Long Mode Segment Limit Enable (LMSLE) bit, to ease virtualization of 64-bit guests.

  • When returning to a non-canonical address using SYSRET, AMD64 processors execute the general protection fault handler in privilege level 3, while on Intel 64 processors it is executed in privilege level 0.

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