You’re really asking about prefetching, not about loop control logic.
In general, loop performance isn’t going to be dictated by the control logic (i.e. the increment/decrement and the condition that gets checked every time through). The time it takes to do these things is inconsequential except in very tight loops. If you’re interested in that, take a look at John Knoeller’s answer for specifics on the 8086’s counter register and why it might’ve been true in the old days that counting down was more efficient. As John says, branch prediction (and also speculation) can play a role in performance here, as can instruction prefetching.
Iteration order can affect performance significantly when it changes the order in which your loop touches memory. The order in which you request memory addresses can affect what is drawn into your cache and also what is evicted from your cache when there is no longer room to fetch new cache lines. Having to go to memory more often than needed is much more expensive than compares, increments, or decrements. On modern CPUs it can take thousands of cycles to get from the processor to memory, and your processor may have to idle for some or all of that time.
You’re probably familiar with caches, so I won’t go into all those details here. What you may not know is that modern processors employ a whole slew of prefetchers to try to predict what data you’re going to need next at different levels of the memory hierarchy. Once they predict, they try to pull that data from memory or lower level caches so that you have what you need when you get around to processing it. Depending on how well they grab what you need next, your performance may or may not improve when using them.
Take a look at Intel’s guide to optimizing for hardware prefetchers. There are four prefetchers listed; two for NetBurst chips:
- NetBurst’s hardware prefetcher can detect streams of memory accesses in either forward or backward directions, and it will try to load data from those locations into the L2 cache.
- NetBurst also has an adjacent cache line (ACL) prefetcher, which will automatically load two adjacent cache lines when you fetch the first one.
and two for Core:
- Core has a slightly more sophisticated hardware prefetcher; it can detect strided access in addition to streams of contiguous references, so it’ll do better if you step through an array every other element, every 4th, etc.
- Core also has an ACL prefetcher like NetBurst.
If you’re iterating through an array forward, you’re going to generate a bunch of sequential, usually contiguous memory references. The ACL prefetchers are going to do much better for forward loops (because you’ll end up using those subsequent cache lines) than for backward loops, but you may do ok making memory references backward if the prefetchers can detect this (as with the hardware prefetchers). The hardware prefetchers on the Core can detect strides, which is helpful for for more sophisticated array traversals.
These simple heuristics can get you into trouble in some cases. For example, Intel actually recommends that you turn off adjacent cache line prefetching for servers, because they tend to make more random memory references than desktop user machines. The probability of not using an adjacent cache line is higher on a server, so fetching data you’re not actually going to use ends up polluting your cache (filling it with unwanted data), and performance suffers. For more on addressing this kind of problem, take a look at this paper from Supercomputing 2009 on using machine learning to tune prefetchers in large data centers. Some guys at Google are on that paper; performance is something that is of great concern to them.
Simple heuristics aren’t going to help you with more sophisticated algorithms, and you might have to start thinking about the sizes of your L1, L2, etc. caches. Image processing, for example, often requires that you perform some operation on subsections of a 2D image, but the order you traverse the image can affect how well useful pieces of it stay in your cache without being evicted. Take a look at Z-order traversals and loop tiling if you’re interested in this sort of thing. It’s a pretty basic example of mapping the 2D locality of image data to the 1D locality of memory to improve performance. It’s also an area where compilers aren’t always able to restructure your code in the best way, but manually restructuring your C code can improve cache performance drastically.
I hope this gives you an idea of how iteration order affects memory performance. It does depend on the particular architecture, but the ideas are general. You should be able to understand prefetching on AMD and Power if you can understand it on Intel, and you don’t really have to know assembly to structure your code to take advantage of memory. You just need to know a little computer architecture.