How has CPU architecture evolution affected virtual function call performance?

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  1. What exactly happens when a skylake CPU mispredicts a branch?
  2. x86 registers: MBR/MDR and instruction registers
  3. What kind of address instruction does the x86 cpu have?
  4. Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
  5. Branch target prediction in conjunction with branch prediction?
  6. Why did Intel change the static branch prediction mechanism over these years?
  7. Are loads and stores the only instructions that gets reordered?
  8. Which cache mapping technique is used in intel core i7 processor?
  9. Globally Invisible load instructions
  10. What happens after a L2 TLB miss?
  11. Slow jmp-instruction
  12. Why do Compilers put data inside .text(code) section of the PE and ELF files and how does the CPU distinguish between data and code?
  13. If I don’t use fences, how long could it take a core to see another core’s writes?
  14. Is LFENCE serializing on AMD processors?
  15. Why is x86 little endian?
  16. Where is the Write-Combining Buffer located? x86
  17. Difference between x86, x32, and x64 architectures?
  18. What are the costs of failed store-to-load forwarding on x86?
  19. What is the difference between Trap and Interrupt?
  20. Is there hardware support for 128bit integers in modern processors?
  21. how are barriers/fences and acquire, release semantics implemented microarchitecturally?
  22. How do the store buffer and Line Fill Buffer interact with each other?
  23. Are load ops deallocated from the RS when they dispatch, complete or some other time?
  24. What specifically marks an x86 cache line as dirty – any write, or is an explicit change required?
  25. Are two store buffer entries needed for split line/page stores on recent Intel?
  26. What is the maximum possible IPC can be achieved by Intel Nehalem Microarchitecture?
  27. Adding a redundant assignment speeds up code when compiled without optimization
  28. Assembly – How to score a CPU instruction by latency and throughput
  29. What is instruction fusion in contemporary x86 processors?
  30. Is processor can do memory and arithmetic operation at the same time?

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