Implementing 64 bit atomic counter with 32 bit atomics

This is a known pattern, called a SeqLock. https://en.wikipedia.org/wiki/Seqlock. (With the simplification that there’s only one writer so no extra support for excluding simultaneous writers is needed.) You don’t need or want the increment of the counter variable itself to use atomic RMW operations. (Unless you’re on a system that can do that cheaply with … Read more

Will two atomic writes to different locations in different threads always be seen in the same order by other threads?

This kind of reordering test is called IRIW (Independent Readers, Independent Writers), where we’re checking if two readers can see the same pair of stores appear in different orders. Related, maybe a duplicate: Acquire/release semantics with 4 threads The very weak C++11 memory model does not require that all threads agree on a global order … Read more