verilog

Verilog: How to instantiate a module

This is all generally covered by Section 23.3.2 of SystemVerilog IEEE Std 1800-2012. The simplest way is to instantiate in the main section of top, creating a named instance and wiring the ports up in order: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0] data_rx_2, output [9:0] data_tx_2 ); subcomponent … Read more

How to interpret blocking vs non blocking assignments in Verilog?

The conventional Verilog wisdom has it all wrong. There is no problem with using blocking assignments for a local variable. However, you should never use blocking assignments for synchronous communication, as this is nondeterministic. A non-blocking assignment within a clocked always block will always infer a flip-flop, as dictated by the semantics. Whether a blocking … Read more

What is `+:` and `-:`?

That particular syntax is called an indexed part select. It’s very useful when you need to select a fixed number of bits from a variable offset within a multi-bit register. Here’s an example of the syntax: reg [31:0] dword; reg [7:0] byte0; reg [7:0] byte1; reg [7:0] byte2; reg [7:0] byte3; assign byte0 = dword[0 … Read more