module TB; reg ***[2:0]*** a, b, c; initial begin a = 3; b = 4; $display ("a = %d, b = %d, c=%d\n", a, b, c); c <= a + b; $display ("a = %d, b = %d, c=%d\n", a, b, c); a <= 10; b <= 2; c = a + b; $display ("a = %d, b = %d, c=%d\n", a, b, c); end endmodule
a=3, b=4 and c=7
Timing Queue of Verilog is divided into four parts:
Active Region -> Inactive -> NBA -> Postponed
Blocking assignments gets evaluated and assign in the ACTIVE region along with $display(). While Nonblocking assignments get evaluated in the ACTIVE region and assign in the NON BLOCKING ASSIGNMENT(NBA) Region. Hence whatever updates made to the a,b,c wont get printed using display statement. You can use $monitor which gets executed in the postponed region.