How come INC instruction of x86 is not atomic? [duplicate]

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Why would it be? The processor core still needs to read the value stored at the memory location, calculate the increment of it, and then store it back. There’s a latency between reading and storing, and in the mean time another operation could have affected that memory location.

Even with out-of-order execution, processor cores are ‘smart’ enough not to trip over their own instructions and wouldn’t be responsible for modifying this memory in the time gap. However, another core could have issued an instruction that modifies that location, a DMA transfer could have affected that location, or other hardware touched that memory location somehow.

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