How instructions are differentiated from data?

by

Simple answer – it doesn’t. Machine code instructions are just binary numbers, as are data. More complicated answer – your processor may (or may not) provide segmentation of memory, meaning that attempting to execute what has been specified as data causes a trap of some sort. This is one of the the meaning of a “segmentation fault” – the processor tried to execute something that was not labelled as being executable code.

More Related Contents:

  1. Can a speculatively executed CPU branch contain opcodes that access RAM?
  2. FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2
  3. Difference between core and processor
  4. Out-of-order instruction execution: is commit order preserved?
  5. What happens after a L2 TLB miss?
  6. Are there any modern CPUs where a cached byte store is actually slower than a word store?
  7. How is load->store reordering possible with in-order commit?
  8. x86 registers: MBR/MDR and instruction registers
  9. On 32-bit CPUs, is an ‘integer’ type more efficient than a ‘short’ type?
  10. How has CPU architecture evolution affected virtual function call performance?
  11. How does the CPU do subtraction?
  12. What kind of address instruction does the x86 cpu have?
  13. Does hardware memory barrier make visibility of atomic operations faster in addition to providing necessary guarantees?
  14. Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
  15. What is a microcoded instruction?
  16. Which cache mapping technique is used in intel core i7 processor?
  17. Adding a redundant assignment speeds up code when compiled without optimization
  18. why we can’t move a 64-bit immediate value to memory?
  19. How does native android code written for ARM run on x86?
  20. Assembly – How to score a CPU instruction by latency and throughput
  21. Getting CPU temperature using Python?
  22. How does x86 pause instruction work in spinlock *and* can it be used in other scenarios?
  23. What is instruction fusion in contemporary x86 processors?
  24. Explicitly accessing banked registers on ARM
  25. Is a mov to a segmentation register slower than a mov to a general purpose register?
  26. Why do we need a bootloader in an embedded device?
  27. How can I get the iOS device CPU architecture in runtime
  28. How to print exact value of the program counter in C
  29. How to get CPU frequency in c#
  30. What is the maximum possible IPC can be achieved by Intel Nehalem Microarchitecture?

Leave a Comment