Assembly – How to score a CPU instruction by latency and throughput

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More Related Contents:

  1. Is performance reduced when executing loops whose uop count is not a multiple of processor width?
  2. Why does breaking the “output dependency” of LZCNT matter?
  3. What is the best way to set a register to zero in x86 assembly: xor, mov or and?
  4. Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
  5. Enhanced REP MOVSB for memcpy
  6. INC instruction vs ADD 1: Does it matter?
  7. How many CPU cycles are needed for each assembly instruction?
  8. Adding a redundant assignment speeds up code when compiled without optimization
  9. Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
  10. Is there a penalty when base+offset is in a different page than the base?
  11. Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
  12. What methods can be used to efficiently extend instruction length on modern x86?
  13. What setup does REP do?
  14. 32-byte aligned routine does not fit the uops cache
  15. Size of store buffers on Intel hardware? What exactly is a store buffer?
  16. Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
  17. Can modern x86 implementations store-forward from more than one prior store?
  18. Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
  19. Modern x86 cost model
  20. Cycles/cost for L1 Cache hit vs. Register on x86?
  21. How can the rep stosb instruction execute faster than the equivalent loop?
  22. Why are loops always compiled into “do…while” style (tail jump)?
  23. Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?
  24. What is the purpose of the EBP frame pointer register?
  25. What happens after a L2 TLB miss?
  26. Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
  27. Are there any modern CPUs where a cached byte store is actually slower than a word store?
  28. Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
  29. Unexpectedly poor and weirdly bimodal performance for store loop on Intel Skylake
  30. Relative performance of x86 inc vs. add instruction

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