int 13h 42h doesn’t load anything in Bochs

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  1. Custom bootloader booted via USB drive produces incorrect output on some computers
  2. Why isn’t my root directory being loaded? (FAT12)
  3. Near call/jump tables don’t always work in a bootloader
  4. Second stage of bootloader prints garbage using Int 0x10/ah=0x0e
  5. BIOS int 10h printing garbage on QEMU
  6. Are loads and stores the only instructions that gets reordered?
  7. How does $ work in NASM, exactly?
  8. Which cache mapping technique is used in intel core i7 processor?
  9. How does x86 paging work?
  10. NASM x86 16-bit addressing modes [duplicate]
  11. is there an inverse instruction to the movemask instruction in intel avx2?
  12. What exactly happens when a skylake CPU mispredicts a branch?
  13. In NASM labels next to each other in memory are printing both strings instead of first one
  14. x86 assembler: floating point compare
  15. Why do Compilers put data inside .text(code) section of the PE and ELF files and how does the CPU distinguish between data and code?
  16. Why can’t you set the instruction pointer directly?
  17. If I don’t use fences, how long could it take a core to see another core’s writes?
  18. x86, difference between BYTE and BYTE PTR
  19. How has CPU architecture evolution affected virtual function call performance?
  20. Assembly difference between [var], and var
  21. NASM Error Parsing, Instruction Expected
  22. Assembly segmentation fault after making a system call, at the end of my code
  23. Fastest way to unpack 32 bits to a 32 byte SIMD vector
  24. Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
  25. Assembly with %include at the top – Printing Outputs Unexpected Result: just an ” S”
  26. What is the difference between Trap and Interrupt?
  27. Load address calculation when using AVX2 gather instructions
  28. How do the store buffer and Line Fill Buffer interact with each other?
  29. Addressing Modes in Assembly Language (IA-32 NASM)
  30. Are two store buffer entries needed for split line/page stores on recent Intel?

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