Memory alignment on a 32-bit Intel processor

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The usual rule of thumb (straight from Intels and AMD’s optimization manuals) is that every data type should be aligned by its own size. An int32 should be aligned on a 32-bit boundary, an int64 on a 64-bit boundary, and so on. A char will fit just fine anywhere.

Another rule of thumb is, of course “the compiler has been told about alignment requirements”. You don’t need to worry about it because the compiler knows to add the right padding and offsets to allow efficient access to data.

The only exception is when working with SIMD instructions, where you have to manually ensure alignment on most compilers.

Secondly, if it is correct, then one
should align data structure members on
an 8 byte boundary. But I’ve seen
people using a 4-byte alignment
instead on these processors.

I don’t see how that makes a difference. The CPU can simply issue a read for the 64-bit block that contains those 4 bytes. That means it either gets 4 extra bytes before the requested data, or after it. But in both cases, it only takes a single read. 32-bit alignment of 32-bit-wide data ensures that it won’t cross a 64-bit boundary.

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