Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs

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  1. Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
  2. What is the best way to set a register to zero in x86 assembly: xor, mov or and?
  3. Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
  4. INC instruction vs ADD 1: Does it matter?
  5. Is performance reduced when executing loops whose uop count is not a multiple of processor width?
  6. Why does breaking the “output dependency” of LZCNT matter?
  7. Is there a penalty when base+offset is in a different page than the base?
  8. Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
  9. What methods can be used to efficiently extend instruction length on modern x86?
  10. 32-byte aligned routine does not fit the uops cache
  11. Size of store buffers on Intel hardware? What exactly is a store buffer?
  12. Can modern x86 implementations store-forward from more than one prior store?
  13. Assembly – How to score a CPU instruction by latency and throughput
  14. Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
  15. Modern x86 cost model
  16. How can the rep stosb instruction execute faster than the equivalent loop?
  17. Why are loops always compiled into “do…while” style (tail jump)?
  18. Enhanced REP MOVSB for memcpy
  19. Adding a redundant assignment speeds up code when compiled without optimization
  20. Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?
  21. Why is this SSE code 6 times slower without VZEROUPPER on Skylake?
  22. Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
  23. What setup does REP do?
  24. Why is SSE scalar sqrt(x) slower than rsqrt(x) * x?
  25. Unexpectedly poor and weirdly bimodal performance for store loop on Intel Skylake
  26. Why can’t my ultraportable laptop CPU maintain peak performance in HPC
  27. How are cache memories shared in multicore Intel CPUs?
  28. Cycles/cost for L1 Cache hit vs. Register on x86?
  29. Return address prediction stack buffer vs stack-stored return address?
  30. Relative performance of x86 inc vs. add instruction

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