Why is this SSE code 6 times slower without VZEROUPPER on Skylake?

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More Related Contents:

  1. Do 128bit cross lane operations in AVX512 give better performance?
  2. Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
  3. Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?
  4. How are x86 uops scheduled, exactly?
  5. Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
  6. Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
  7. 32-byte aligned routine does not fit the uops cache
  8. Non-temporal loads and the hardware prefetcher, do they work together?
  9. Size of store buffers on Intel hardware? What exactly is a store buffer?
  10. Why is SSE scalar sqrt(x) slower than rsqrt(x) * x?
  11. Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
  12. Fast vectorized rsqrt and reciprocal with SSE/AVX depending on precision
  13. Loop unrolling to achieve maximum throughput with Ivy Bridge and Haswell
  14. Why can’t my ultraportable laptop CPU maintain peak performance in HPC
  15. Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
  16. latency vs throughput in intel intrinsics
  17. How are cache memories shared in multicore Intel CPUs?
  18. Return address prediction stack buffer vs stack-stored return address?
  19. Efficient sse shuffle mask generation for left-packing byte elements
  20. Is performance reduced when executing loops whose uop count is not a multiple of processor width?
  21. Why does breaking the “output dependency” of LZCNT matter?
  22. What are the best instruction sequences to generate vector constants on the fly?
  23. What is the purpose of the EBP frame pointer register?
  24. Vectorizing with unaligned buffers: using VMASKMOVPS: generating a mask from a misalignment count? Or not using that insn at all
  25. Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
  26. Is using double faster than float?
  27. x86_64: is IMUL faster than 2x SHL + 2x ADD?
  28. AVX/SSE version of xorshift128+
  29. Per-element atomicity of vector load/store and gather/scatter?
  30. How can the rep stosb instruction execute faster than the equivalent loop?

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