packed vs unpacked vectors in system verilog

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This article gives more details about this issue:
http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.

A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

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