RCX, along with R11, is used by the syscall instruction, being immediately destroyed by it. Thus these registers are not only not saved after syscall, but they can’t even be used for parameter passing. Thus R10 was chosen to replace unusable RCX to pass fourth parameter. See also this answer for a bit more information … Read more
History note: Intel implemented their 64-bit ISA, which they called IA-64 which was a complete replacement of the 32-bit x86 ISA, in their Itanium line of processors. IA-64 wasn’t backward compatible with x86 and never really became popular outside the high-end server market. AMD created the AMD64 ISA as an incremental evolution over the x86 … Read more
What is so special about lea that mov can’t do? mov reg,imm loads an immediate constant into its destination operand. Immediate constant is encoded directly in the opcode, e.g. mov eax,someVar would be encoded as B8 EF CD AB 00 if address of someVar is 0x00ABCDEF. I.e. to encode such an instruction with imm being … Read more
Yes rounding errors, and it is effectively NOT the same hardware. The 32 bit version is targeting a different set of instructions and register sizes.
This optimization has since been implemented in GCC. It can be enabled with the -fno-plt option and the noplt function attribute: Do not use the PLT for external function calls in position-independent code. Instead, load the callee address at call sites from the GOT and branch to it. This leads to more efficient code by … Read more
How to convert Linux 32-bit gcc inline assembly to 64-bit code? [closed]
Currently no implementation of x86 (or any other ISA, as far as I know) supports optimizing silent stores. There has been academic research on this and there is even a patent on “eliminating silent store invalidation propagation in shared memory cache coherency protocols”. (Googling ‘”silent store” cache’ if you are interested in more.) For x86, … Read more
Yes, the ISA is a document / specification, not hardware. Implementing all of it correctly is what makes something an x86 CPU, rather than just something with similarities to x86. See the x86 tag wiki for links to the official docs (Intel’s manuals). Intel and AMD’s implementations of the x86 ISA differ mainly in performance, … Read more
I had a response on the cfe-dev (clang front end developers’ list) from one of the developers: LLVM currently always spills “rm” constraints in order to simplify the handling of inline asm in the backend (you can ask on llvmdev if you want details). I don’t know of any plans to fix this in the … Read more
Summary: try to allocate memory near your static code. But for calls that can’t reach with rel32, fall back to call qword [rel pointer] or inline mov r64,imm64 / call r64. Your mechanism 5. is probably best for performance if you can’t make 2. work, but 4. is easy and should be fine. Direct call … Read more