Fastest inline-assembly spinlock

by

Although there is already an accepted answer, there are a few things that where missed that could be used to improve all the answers, taken from this Intel article, all above fast lock implementation:

  1. Spin on a volatile read, not an atomic instruction, this avoids unneeded bus locking, especially on highly contended locks.
  2. Use back-off for highly contested locks
  3. Inline the lock, preferably with intrinsics for compilers where inline asm is detrimental (basically MSVC).

More Related Contents:

  1. Why does C++ code for testing the Collatz conjecture run faster than hand-written assembly?
  2. Can modern x86 hardware not store a single byte to memory?
  3. Locks around memory manipulation via inline assembly
  4. Replacing a 32-bit loop counter with 64-bit introduces crazy performance deviations with _mm_popcnt_u64 on Intel CPUs
  5. Why does this function push RAX to the stack as the first operation?
  6. When should I use _mm_sfence _mm_lfence and _mm_mfence
  7. What C/C++ compiler can use push pop instructions for creating local variables, instead of just increasing esp once?
  8. Atomicity on x86
  9. How do objects work in x86 at the assembly level?
  10. How do I call “cpuid” in Linux?
  11. What does the “lock” instruction mean in x86 assembly?
  12. Difference in performance between MSVC and GCC for highly optimized matrix multplication code
  13. Atomic operations, std::atomic and ordering of writes
  14. Why does a std::atomic store with sequential consistency use XCHG?
  15. How to generate assembly code with clang in Intel syntax?
  16. C++ How is release-and-acquire achieved on x86 only using MOV?
  17. Assembly ADC (Add with carry) to C++
  18. How does a mutex lock and unlock functions prevents CPU reordering?
  19. Does hardware memory barrier make visibility of atomic operations faster in addition to providing necessary guarantees?
  20. x86 MUL Instruction from VS 2008/2010
  21. Address of function is not actual code address
  22. What are these seemingly-useless callq instructions in my x86 object files for?
  23. Atomicity of loads and stores on x86
  24. Why is this SIMD multiplication not faster than non-SIMD multiplication?
  25. Why is integer assignment on a naturally aligned variable atomic on x86?
  26. Is < faster than
  27. Can I use Intel syntax of x86 assembly with GCC?
  28. Stack allocation, padding, and alignment
  29. inlining failed in call to always_inline ‘__m256d _mm256_broadcast_sd(const double*)’
  30. Bit popcount for large buffer, with Core 2 CPU (SSSE3)

Leave a Comment