How to write a disassembler? [closed]

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  1. Are loads and stores the only instructions that gets reordered?
  2. Which cache mapping technique is used in intel core i7 processor?
  3. How does x86 paging work?
  4. Globally Invisible load instructions
  5. is there an inverse instruction to the movemask instruction in intel avx2?
  6. What exactly happens when a skylake CPU mispredicts a branch?
  7. x86 assembler: floating point compare
  8. Why do Compilers put data inside .text(code) section of the PE and ELF files and how does the CPU distinguish between data and code?
  9. Why can’t you set the instruction pointer directly?
  10. What does “DS:[40207A]” mean in assembly?
  11. If I don’t use fences, how long could it take a core to see another core’s writes?
  12. How to efficiently convert an 8-bit bitmap to array of 0/1 integers with x86 SIMD [duplicate]
  13. Sum reduction of unsigned bytes without overflow, using SSE2 on Intel
  14. How has CPU architecture evolution affected virtual function call performance?
  15. The most correct way to refer to 32-bit and 64-bit versions of programs for x86-related CPUs?
  16. How to interpret objdump disassembly output columns?
  17. int 13h 42h doesn’t load anything in Bochs
  18. Get size of assembly instructions
  19. Fastest way to unpack 32 bits to a 32 byte SIMD vector
  20. Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
  21. What is the difference between Trap and Interrupt?
  22. Is there hardware support for 128bit integers in modern processors?
  23. Load address calculation when using AVX2 gather instructions
  24. How to access the control registers cr0,cr2,cr3 from a program? Getting segmentation fault
  25. How do the store buffer and Line Fill Buffer interact with each other?
  26. Are load ops deallocated from the RS when they dispatch, complete or some other time?
  27. Bubble sort in x86 (masm32), the sort I wrote doesn’t work
  28. SAR command in X86 assembly with one parameter
  29. Are two store buffer entries needed for split line/page stores on recent Intel?
  30. How does the CPU know how many bytes it should read for the next instruction, considering instructions have different lengths?

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