No, [RIP + rel32] is the only addressing mode involving RIP. See also Referencing the contents of a memory location. (x86 addressing modes). If you want maximum efficiency for indexing a static array, you need to make position-dependent code so you can use the table address as a 32-bit absolute disp32 in a normal addressing … Read more
In NASM syntax, that instruction should be MOV EBX, MY_TABLE. What MOV EBX, [MY_TABLE] would do is load the first 4 bytes located at MY_TABLE into EBX. Another alternative would be to use LEA, as in LEA EBX, [MY_TABLE]. In this case the tutorial is right. MY_TABLE is defined as an array of words. A … Read more
No, you cannot use 8-bit or 16-bit registers in addressing calculations in 64-bit mode, nor can you use 8-bit registers in 32-bit mode. You can use 16-bit registers in 32-bit mode, and 32-bit registers in 64-bit mode, via use of the 0x67 address size prefix byte. (But using a narrower register makes the whole address … Read more
RIP addressing is always relative to RIP (64bit Instruction Pointer) register. So it can be use for global variables only. The 0 offset is equal to address of the following instruction after the RIP-addressed instruction. For example: mov al,[rip+2] al=53 jmp short next (length=2 bytes) db 53 next: mov bl,[rip-7] (length=6 bytes) bl=53 You wouldn’t … Read more
I’m curious as to why we are not allowed to use registers as offsets in MIPS. I’m not sure if you mean “why does MIPS assembly not permit you to write it this form” or “why does the underlying ISA not offer this form”. If it’s the former, then the answer is that the base … Read more
It’s AT&T assembly syntax: source comes before destination mnemonic suffixes indicate the size of the operands (q for quad, etc.) registers are prefixed with % and immediate values with $ effective addresses are in the form DISP(BASE, INDEX, SCALE) (DISP + BASE + INDEX * SCALE) Indirect jump/call operands indicated with * (as opposed to … Read more
I believe that you want to load the address of your string into %rsi; your code attempts to load a quadword from that address rather than the address itself. You want: lea msg(%rip), %rsi if I’m not mistaken. I don’t have a linux box to test on, however.
The next. That’s a general rule on x86 (see also branches). In Intel’s manual volume 2 section 2.2.1.6 RIP-Relative Addressing: A new addressing form, RIP-relative (relative instruction-pointer) addressing, is implemented in 64-bit mode. An effective address is formed by adding displacement to the 64-bit RIP of the next instruction.
The complete memory addressing mode format in AT&T assembly is: offset(base, index, width) So for your case: offset = 0 base = ebx index = eax width = 4 Meaning that the instruction is something like: eax = *(uint32_t *)((uint8_t *)ebx + eax * 4 + 0) In a C-like pseudocode.