Extensions that introduce new architectural state require special OS support, because the OS has to save/restore restore more data on context switches. So from the OSes perspective, there’s nothing extra it needs to do to let user-space code run SSSE3 instructions, if the OS supports SSE. SSE, AVX, and AVX512 are the extensions that introduced … Read more
For anyone else who might reach this question, I think this C++ code implements correctly 4 xorshift128plus generators running in parallel, using AVX2: __m256i xorshift128plus_avx2(__m256i &state0, __m256i &state1) { __m256i s1 = state0; const __m256i s0 = state1; state0 = s0; s1 = _mm256_xor_si256(s1, _mm256_slli_epi64(s1, 23)); state1 = _mm256_xor_si256(_mm256_xor_si256(_mm256_xor_si256(s1, s0), _mm256_srli_epi64(s1, 18)), _mm256_srli_epi64(s0, 5)); return … Read more
I realise that this is an old question and that the person who asked it appears to be no longer around, but I hit the same problem yesterday. Here’s what I worked out. When compiled both your sse2.cpp and avx.cpp files produce object files that not only contain your function but also any required template … Read more
Most compilers will automatically define: __SSE__ __SSE2__ __SSE3__ __AVX__ __AVX2__ etc, according to whatever command line switches you are passing. You can easily check this with gcc (or gcc-compatible compilers such as clang), like this: $ gcc -msse3 -dM -E – < /dev/null | egrep “SSE|AVX” | sort #define __SSE__ 1 #define __SSE2__ 1 #define … Read more
This version should be optimal for both Intel Sandy/Ivy Bridge and AMD Bulldozer, and later CPUs. // x = ( x7, x6, x5, x4, x3, x2, x1, x0 ) float sum8(__m256 x) { // hiQuad = ( x7, x6, x5, x4 ) const __m128 hiQuad = _mm256_extractf128_ps(x, 1); // loQuad = ( x3, x2, x1, … Read more