Is vxorps-zeroing on AMD Jaguar/Bulldozer/Zen faster with xmm registers than ymm?

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  1. How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent
  2. Test whether a register is zero with CMP reg,0 vs OR reg,reg?
  3. What are the best instruction sequences to generate vector constants on the fly?
  4. What does `rep ret` mean?
  5. Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
  6. Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
  7. Using ymm registers as a “memory-like” storage location
  8. “enter” vs “push ebp; mov ebp, esp; sub esp, imm” and “leave” vs “mov esp, ebp; pop ebp”
  9. Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?
  10. How to force NASM to encode [1 + rax*2] as disp32 + index*2 instead of disp8 + base + index?
  11. Does using xor reg, reg give advantage over mov reg, 0? [duplicate]
  12. Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?
  13. Micro fusion and addressing modes
  14. Why does mulss take only 3 cycles on Haswell, different from Agner’s instruction tables? (Unrolling FP loops with multiple accumulators)
  15. Custom bootloader booted via USB drive produces incorrect output on some computers
  16. rbp not allowed as SIB base?
  17. What C/C++ compiler can use push pop instructions for creating local variables, instead of just increasing esp once?
  18. execve shellcode writing segmentation fault
  19. double condition checking in assembly
  20. Can modern x86 implementations store-forward from more than one prior store?
  21. Printing hex values in x86 assembly
  22. What does the dollar sign ($) mean in x86 assembly when calculating string lengths like “$ – label”? [duplicate]
  23. Why not store function parameters in XMM vector registers?
  24. Assembly – How to score a CPU instruction by latency and throughput
  25. What is instruction fusion in contemporary x86 processors?
  26. call subroutines conditionally in assembly
  27. Can PTEST be used to test if two registers are both zero or some other condition?
  28. Cannot move 8 bit address to 16 bit register
  29. Is a mov to a segmentation register slower than a mov to a general purpose register?
  30. Addressing Modes in Assembly Language (IA-32 NASM)

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