You did a great job with your level of commenting, style, and the program layout. Some of the best I’ve seen on SO. Overall, a good effort. However, there were bugs. I’ve produced an annotated version of your code and a refactored one. See below. There were a number of bugs throughout the code, not … Read more
TL:DR: MARS tooltips are misleading; you need to disable auto-alignment for the rest of the section using .align 0. You can’t just under-align the next word. .align 1 does align by 2, that’s not the problem. e.g. try it between .byte or .ascii pseudo-instructions. e.g. this source produces 0x00110062 as the first word of the … Read more
The strings you print with syscall 4 need to be ASCIIZ, i.e. ASCII with a zero terminator. So you need to store a byte with the value zero after the last character in each string. And to be able to store that extra byte, you need to reserve one additional byte for each string (i.e. … Read more
You’re missing the 32 bit libc dev package: On Ubuntu it’s called libc6-dev-i386 – do sudo apt-get install libc6-dev-i386. See below for extra instructions for Ubuntu 12.04. On Red Hat distros, the package name is glibc-devel.i686 (Thanks to David Gardner’s comment). On CentOS 5.8, the package name is glibc-devel.i386 (Thanks to JimKleck’s comment). On CentOS … Read more
TL:DR: Classic MIPS I checks branch conditions in the first half cycle of EX, so forwarding to them is not special. IF only needs the address in the 2nd half of a cycle so EX can forward to it. These factors combine to give only 1 cycle of branch latency (hidden by 1 delay slot), … Read more
GCC can produce assembly code for a large number of architectures, include MIPS. But what architecture a given GCC instance targets is decided when GCC itself is compiled. The precompiled binary you will find in an Ubuntu system knows about x86 (possibly both 32-bit and 64-bit modes) but not MIPS. Compiling GCC with a target … Read more
(In the diagrams and text below, PC is the address of the branch instruction itself. PC+4 is the end of the branch instruction itself, and the start of the branch delay slot. Except in the absolute jump diagram.) 1. Branch Address Calculation In MIPS branch instruction has only 16 bits offset to determine next instruction. … Read more
(thanks for posting it). You appear to be using this definition of system calls (https://www.assemblylanguagetuts.com/mips-syscall-services-table/) Just after the beq instruction in the while: loop, you increment $s1. I recall that MIPS cpus had a timing bug where it always executed the instruction following a branch. Here, that would mean that $s1 would be one more … Read more
You could use this http://reliant.colab.duke.edu/c2mips/ trans of c to Mips assembly. And the following should be work. .file 1 “” .section .mdebug.abi32 .previous .gnu_attribute 4, 1 .abicalls .rdata .align 2 $LC0: .ascii “Input the string: \000” .align 2 $LC1: .ascii “%s\000” .align 2 $LC2: .ascii “*%s*\012\000” .text .align 2 .globl main $LFB0 = . .set … Read more