Arithmetic identities and EFLAGS

by

No, they’re not equivalent. For instance if rax = 1 and rcx = 3, then sub rax, rcx will set the carry flag, because you are subtracting a larger number from a smaller one. But in your second sequence of instructions, following add rax, temp, rax will contain -3 (i.e. 0xfffffffffffffffd), and adding 1 to -3 does not cause a carry. So after your second sequence of instructions, the carry flag would be cleared.

I do not know of any simple way to exactly emulate the behavior of sub including its effect on flags (other than by using cmp, but that’s cheating because it’s really just sub under the hood). In principle, you could write a long sequence of instructions that manually did all the same tests that sub does internally (referring to its precise description in the instruction set manual), and sets the flags at the end using sahf or popf of the like.

This would be a lot of work, especially if you are not going to use cmp, and I am not going to go through it for this answer. Especially because I also can’t think of any reason why one would need to do it, except as a fairly pointless exercise.

More Related Contents:

  1. Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register?
  2. What’s the purpose of the LEA instruction?
  3. Why doesn’t GCC use partial registers?
  4. rbp not allowed as SIB base?
  5. Assembly – JG/JNLE/JL/JNGE after CMP
  6. Why are signed and unsigned multiplication different instructions on x86(-64)?
  7. What do the E and R prefixes stand for in the names of Intel 32-bit and 64-bit registers?
  8. Why is (or isn’t?) SFENCE + LFENCE equivalent to MFENCE?
  9. Why is imul used for multiplying unsigned numbers?
  10. What are the names of the new X86_64 processors registers?
  11. x64 instruction encoding and the ModRM byte
  12. Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?
  13. Why not store function parameters in XMM vector registers?
  14. How to read and write x86 flags registers directly?
  15. How to multiply a register by 37 using only 2 consecutive leal instructions in x86?
  16. What does “rep; nop;” mean in x86 assembly? Is it the same as the “pause” instruction?
  17. When should I use size directives in x86?
  18. Carry Flag, Auxiliary Flag and Overflow Flag in Assembly
  19. Using 8-bit registers in x86-64 indexed addressing modes
  20. x86 32 bit opcodes that differ in x86-x64 or entirely removed
  21. Why can I access lower dword/word/byte in a register but not higher?
  22. What is callq instruction?
  23. What is the compatible subset of Intel’s and AMD’s x86-64 implementations?
  24. x86 Assembly pushl/popl don’t work with “Error: suffix or operands invalid”
  25. What considerations go into predicting latency for operations on modern superscalar processors and how can I calculate them by hand?
  26. What is the stack engine in the Sandybridge microarchitecture?
  27. Assembly registers in 64-bit architecture
  28. Random number in emu8086 without using DOS/BIOS calls?
  29. Why is the Carry Flag set during a subtraction when zero is the minuend?
  30. how does push and pop work in assembly

Leave a Comment