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- Does the Intel Memory Model make SFENCE and LFENCE redundant?
- Why is (or isn’t?) SFENCE + LFENCE equivalent to MFENCE?
- Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register?
- What’s the purpose of the LEA instruction?
- Why doesn’t GCC use partial registers?
- rbp not allowed as SIB base?
- Why are signed and unsigned multiplication different instructions on x86(-64)?
- What do the E and R prefixes stand for in the names of Intel 32-bit and 64-bit registers?
- Why is imul used for multiplying unsigned numbers?
- Does a memory barrier ensure that the cache coherence has been completed?
- What are the names of the new X86_64 processors registers?
- x64 instruction encoding and the ModRM byte
- Why not store function parameters in XMM vector registers?
- Why flush the pipeline for Memory Order Violation caused by other logical processors?
- How to multiply a register by 37 using only 2 consecutive leal instructions in x86?
- Which is a better write barrier on x86: lock+addl or xchgl?
- What does “rep; nop;” mean in x86 assembly? Is it the same as the “pause” instruction?
- When should I use size directives in x86?
- Using 8-bit registers in x86-64 indexed addressing modes
- x86 32 bit opcodes that differ in x86-x64 or entirely removed
- Why can I access lower dword/word/byte in a register but not higher?
- Arithmetic identities and EFLAGS
- What is callq instruction?
- What is the compatible subset of Intel’s and AMD’s x86-64 implementations?
- x86 Assembly pushl/popl don’t work with “Error: suffix or operands invalid”
- How to make the kernel for my bootloader?
- Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
- What do the brackets mean in NASM syntax for x86 asm?
- What’s difference between number with $ or without $ symbol in at&t assembly syntax?
- Is processor can do memory and arithmetic operation at the same time?