What happens when different CPU cores write to the same RAM address without synchronization?
x86 (like every other mainstream SMP CPU architecture) has coherent data caches. It’s impossible for two difference caches (e.g. L1D of 2 different cores) to hold conflicting data for the same cache line. The hardware imposes an order (by some implementation-specific mechanism to break ties in case two requests for ownership arrive in the same … Read more