What happens when different CPU cores write to the same RAM address without synchronization?

x86 (like every other mainstream SMP CPU architecture) has coherent data caches. It’s impossible for two difference caches (e.g. L1D of 2 different cores) to hold conflicting data for the same cache line. The hardware imposes an order (by some implementation-specific mechanism to break ties in case two requests for ownership arrive in the same … Read more

Which is faster: x

Potentially depends on the CPU. However, all modern CPUs (x86, ARM) use a “barrel shifter” — a hardware module specifically designed to perform arbitrary shifts in constant time. So the bottom line is… no. No difference.

How are 3D arrays stored in C?

At a low level, there is no such thing as a multi-dimensional array. There is just a flat block of memory, large enough to hold a given number of elements. In C, a multi-dimensional array is conceptually an array whose elements are also arrays. So if you do: int array[2][3]; Conceptually you end up with: … Read more

Divide by 10 using bit shifts?

Editor’s note: this is not actually what compilers do, and gives the wrong answer for large positive integers ending with 9, starting with div10(1073741829) = 107374183 not 107374182. It is exact for smaller inputs, though, which may be sufficient for some uses. Compilers (including MSVC) do use fixed-point multiplicative inverses for constant divisors, but they … Read more