How to force NASM to encode [1 + rax*2] as disp32 + index*2 instead of disp8 + base + index?

by

NOSPLIT:

Similarly, NASM will split [eax*2] into [eax+eax] because that allows the offset field to be absent and space to be saved; in fact, it will also split [eax*2+offset] into [eax+eax+offset].
You can combat this behaviour by the use of the NOSPLIT keyword: [nosplit eax*2] will force [eax*2+0] to be generated literally.
[nosplit eax*1] also has the same effect. In another way, a split EA form [0, eax*2] can be used, too. However, NOSPLIT in [nosplit eax+eax] will be ignored because user’s intention here is considered as [eax+eax].

lea eax, [NOSPLIT 1+rax*2]
lea eax, [1+rax*2]

00000000  8D044501000000    lea eax,[rax*2+0x1]
00000007  8D440001          lea eax,[rax+rax+0x1]

More Related Contents:

  1. How do I print an integer in Assembly Level Programming without printf from the c library?
  2. How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent
  3. Test whether a register is zero with CMP reg,0 vs OR reg,reg?
  4. NASM Assembly convert input to integer?
  5. How does $ work in NASM, exactly?
  6. NASM x86 16-bit addressing modes [duplicate]
  7. rbp not allowed as SIB base?
  8. How to read the Intel Opcode notation
  9. Basic use of immediates vs. square brackets in YASM/NASM x86 assembly
  10. What does `rep ret` mean?
  11. How to load a single byte from address in assembly
  12. In NASM labels next to each other in memory are printing both strings instead of first one
  13. Why isn’t my root directory being loaded? (FAT12)
  14. Why NASM on Linux changes registers in x86_64 assembly
  15. x86, difference between BYTE and BYTE PTR
  16. Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
  17. What do the brackets mean in NASM syntax for x86 asm?
  18. Segmentation fault when using DB (define byte) inside a function
  19. Assembly difference between [var], and var
  20. NASM Error Parsing, Instruction Expected
  21. How to tell the length of an x86 instruction?
  22. Convert string to int. x86 32 bit Assembler using Nasm
  23. Get size of assembly instructions
  24. Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?
  25. How to tell the length of an x86 instruction?
  26. Second stage of bootloader prints garbage using Int 0x10/ah=0x0e
  27. Does using xor reg, reg give advantage over mov reg, 0? [duplicate]
  28. Addressing Modes in Assembly Language (IA-32 NASM)
  29. Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?
  30. Solution needed for building a static IDT and GDT at assemble/compile/link time

Leave a Comment