Test whether a register is zero with CMP reg,0 vs OR reg,reg?

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  1. What is the best way to set a register to zero in x86 assembly: xor, mov or and?
  2. How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent
  3. What does `rep ret` mean?
  4. What methods can be used to efficiently extend instruction length on modern x86?
  5. Does the Intel Memory Model make SFENCE and LFENCE redundant?
  6. Can modern x86 implementations store-forward from more than one prior store?
  7. Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
  8. Is vxorps-zeroing on AMD Jaguar/Bulldozer/Zen faster with xmm registers than ymm?
  9. “enter” vs “push ebp; mov ebp, esp; sub esp, imm” and “leave” vs “mov esp, ebp; pop ebp”
  10. Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?
  11. How to force NASM to encode [1 + rax*2] as disp32 + index*2 instead of disp8 + base + index?
  12. In what situation would the AVX2 gather instructions be faster than individually loading the data?
  13. Does using xor reg, reg give advantage over mov reg, 0? [duplicate]
  14. How can the rep stosb instruction execute faster than the equivalent loop?
  15. Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?
  16. What is the trick to learn x86 assembly language on Windows PC? [closed]
  17. 8086 assembly on DOSBox: Bug with idiv instruction?
  18. What is a Partial Flag Stall?
  19. Why are signed and unsigned multiplication different instructions on x86(-64)?
  20. Does a memory barrier ensure that the cache coherence has been completed?
  21. What is the 0x10 in the “leal 0x10(%ebx), %eax” x86 assembly instruction?
  22. What does the bracket in `movl (%eax), %eax` mean?
  23. Spinlock with XCHG unlocking
  24. Which is a better write barrier on x86: lock+addl or xchgl?
  25. X86 prefetching optimizations: “computed goto” threaded code
  26. What are the ESP and the EBP registers?
  27. What is the penalty of mixing EVEX and VEX encoded scheme?
  28. x86 Assembly – Why is [e]bx preserved in calling conventions?
  29. How to know if an assembly code has particular syntax (emu8086, NASM, TASM, …)?
  30. Assembly bubble sort swap

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