How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent

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  1. Micro fusion and addressing modes
  2. What is the stack engine in the Sandybridge microarchitecture?
  3. What is a Partial Flag Stall?
  4. Slow jmp-instruction
  5. Why does Intel hide internal RISC core in their processors?
  6. Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?
  7. Can x86’s MOV really be “free”? Why can’t I reproduce this at all?
  8. Test whether a register is zero with CMP reg,0 vs OR reg,reg?
  9. Is performance reduced when executing loops whose uop count is not a multiple of processor width?
  10. Why isn’t movl from memory to memory allowed?
  11. Why does breaking the “output dependency” of LZCNT matter?
  12. What is the “FS”/”GS” register intended for?
  13. What does `rep ret` mean?
  14. Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
  15. Size of store buffers on Intel hardware? What exactly is a store buffer?
  16. What was the original reason for the design of AT&T assembly syntax?
  17. Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
  18. What’s the purpose of the rotate instructions (ROL, RCL on x86)?
  19. Is there a complete x86 assembly language reference that uses AT&T syntax? [closed]
  20. Why flush the pipeline for Memory Order Violation caused by other logical processors?
  21. Is vxorps-zeroing on AMD Jaguar/Bulldozer/Zen faster with xmm registers than ymm?
  22. “enter” vs “push ebp; mov ebp, esp; sub esp, imm” and “leave” vs “mov esp, ebp; pop ebp”
  23. Why isn’t the instruction pointer a normal register usable with MOV or ADD?
  24. What are the costs of failed store-to-load forwarding on x86?
  25. How to force NASM to encode [1 + rax*2] as disp32 + index*2 instead of disp8 + base + index?
  26. x86 32 bit opcodes that differ in x86-x64 or entirely removed
  27. Where is VPERMB in AVX2?
  28. Does using xor reg, reg give advantage over mov reg, 0? [duplicate]
  29. Are two store buffer entries needed for split line/page stores on recent Intel?
  30. Is processor can do memory and arithmetic operation at the same time?

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