No, [RIP + rel32] is the only addressing mode involving RIP. See also Referencing the contents of a memory location. (x86 addressing modes). If you want maximum efficiency for indexing a static array, you need to make position-dependent code so you can use the table address as a 32-bit absolute disp32 in a normal addressing … Read more
NASM/YASM is easy to distinguish from MASM/TASM/emu8086. YASM uses NASM syntax, with a few minor differences in what it accepts for constants and directives. I don’t know how to distinguish MASM from TASM, or TASM from emu8086, or FASM, so I’ll leave that for another answer to address. In NASM, explicit sizes on things like … Read more
Yes all “normal” ISAs including 8080 and x86 guarantee that instructions are atomic with respect to interrupts on the same core. Either an instruction has fully executed and all its architectural effects are visible (in the interrupt handler), or none of them are. Any deviations from this rule are generally carefully documented. For example, Intel’s … Read more
The simple way is to just read one byte, decode it and then determine if it’s a complete instruction. If not read another byte, decode it if necessary and then determine if a complete instruction has been read. If not continue reading/decoding bytes until the complete instruction is read. This means that if the instruction … Read more
Your analysis is not correct. Actually is CPU ALU unit dependent. 🙂 In first case you are using 4 bit integer but you forgotten that the highest bit of 4 bit sign integer is sign! So you are checking only the Carry and Overflow status and not also Negative status bit. In generally binary arithmetic … Read more
Related: Does a compiler always produce an assembly code? – more about why some compilers do compile only to asm, instead of straight to machine code in some object file format. There are several reasons that compiling to asm instead of machine code makes a compiler’s job easier and a compiler more easily portable. But … Read more
The CPU does not know nor does it care. Instead, bits in the Flags register are set on certain operations, and how your program acts on those flags depends on what the source code told it to. E.g., mov eax, 0FFFFFFFFh test eax, eax js isNegative vs. mov eax, 0FFFFFFFFh test eax, eax jb isNegative … Read more
History note: Intel implemented their 64-bit ISA, which they called IA-64 which was a complete replacement of the 32-bit x86 ISA, in their Itanium line of processors. IA-64 wasn’t backward compatible with x86 and never really became popular outside the high-end server market. AMD created the AMD64 ISA as an incremental evolution over the x86 … Read more
What is so special about lea that mov can’t do? mov reg,imm loads an immediate constant into its destination operand. Immediate constant is encoded directly in the opcode, e.g. mov eax,someVar would be encoded as B8 EF CD AB 00 if address of someVar is 0x00ABCDEF. I.e. to encode such an instruction with imm being … Read more
No, a vpcmpeqb into a mask register does not trigger slow mode if you use a zmm register as one of the comparands, at least on SKX. This is also true of any of any other instruction (as far as I tested) which only reads the key 512-bit registers (the key registers being zmm0 – … Read more