Why is SSE scalar sqrt(x) slower than rsqrt(x) * x?

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  3. Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
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  12. Is there a penalty when base+offset is in a different page than the base?
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  16. What methods can be used to efficiently extend instruction length on modern x86?
  17. What setup does REP do?
  18. 32-byte aligned routine does not fit the uops cache
  19. Non-temporal loads and the hardware prefetcher, do they work together?
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  22. Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
  23. Can modern x86 implementations store-forward from more than one prior store?
  24. Assembly – How to score a CPU instruction by latency and throughput
  25. Unexpectedly poor and weirdly bimodal performance for store loop on Intel Skylake
  26. Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
  27. latency vs throughput in intel intrinsics
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  29. Efficient sse shuffle mask generation for left-packing byte elements
  30. How can the rep stosb instruction execute faster than the equivalent loop?

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