x86_64: is IMUL faster than 2x SHL + 2x ADD?

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More Related Contents:

  1. Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
  2. Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
  3. Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
  4. 32-byte aligned routine does not fit the uops cache
  5. Size of store buffers on Intel hardware? What exactly is a store buffer?
  6. Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
  7. Unexpectedly poor and weirdly bimodal performance for store loop on Intel Skylake
  8. Performance optimisations of x86-64 assembly – Alignment and branch prediction
  9. What is the best way to set a register to zero in x86 assembly: xor, mov or and?
  10. Why are loops always compiled into “do…while” style (tail jump)?
  11. Enhanced REP MOVSB for memcpy
  12. INC instruction vs ADD 1: Does it matter?
  13. Adding a redundant assignment speeds up code when compiled without optimization
  14. Why is Skylake so much better than Broadwell-E for single-threaded memory throughput?
  15. Why is this SSE code 6 times slower without VZEROUPPER on Skylake?
  16. Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
  17. Is there a penalty when base+offset is in a different page than the base?
  18. What methods can be used to efficiently extend instruction length on modern x86?
  19. Why is SSE scalar sqrt(x) slower than rsqrt(x) * x?
  20. Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
  21. Why is imul used for multiplying unsigned numbers?
  22. Can modern x86 implementations store-forward from more than one prior store?
  23. Assembly – How to score a CPU instruction by latency and throughput
  24. Why can’t my ultraportable laptop CPU maintain peak performance in HPC
  25. How are cache memories shared in multicore Intel CPUs?
  26. Modern x86 cost model
  27. Return address prediction stack buffer vs stack-stored return address?
  28. Relative performance of x86 inc vs. add instruction
  29. How can the rep stosb instruction execute faster than the equivalent loop?
  30. Do 128bit cross lane operations in AVX512 give better performance?

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