What is the purpose of the EBP frame pointer register?

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  1. What is the best way to set a register to zero in x86 assembly: xor, mov or and?
  2. Why is the loop instruction slow? Couldn’t Intel have implemented it efficiently?
  3. Enhanced REP MOVSB for memcpy
  4. INC instruction vs ADD 1: Does it matter?
  5. How many CPU cycles are needed for each assembly instruction?
  6. Adding a redundant assignment speeds up code when compiled without optimization
  7. Is performance reduced when executing loops whose uop count is not a multiple of processor width?
  8. Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
  9. Why does breaking the “output dependency” of LZCNT matter?
  10. Is there a penalty when base+offset is in a different page than the base?
  11. Branch alignment for loops involving micro-coded instructions on Intel SnB-family CPUs
  12. Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
  13. What methods can be used to efficiently extend instruction length on modern x86?
  14. What setup does REP do?
  15. 32-byte aligned routine does not fit the uops cache
  16. Is ADD 1 really faster than INC ? x86 [duplicate]
  17. Size of store buffers on Intel hardware? What exactly is a store buffer?
  18. Why is SSE scalar sqrt(x) slower than rsqrt(x) * x?
  19. Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
  20. Can modern x86 implementations store-forward from more than one prior store?
  21. Assembly – How to score a CPU instruction by latency and throughput
  22. Unexpectedly poor and weirdly bimodal performance for store loop on Intel Skylake
  23. Is it useful to use VZEROUPPER if your program+libraries contain no SSE instructions?
  24. Modern x86 cost model
  25. Relative performance of x86 inc vs. add instruction
  26. How can the rep stosb instruction execute faster than the equivalent loop?
  27. Why is this SSE code 6 times slower without VZEROUPPER on Skylake?
  28. What are the latency and throughput costs of producer-consumer sharing of a memory location between hyper-siblings versus non-hyper siblings?
  29. How can I accurately benchmark unaligned access speed on x86_64?
  30. Do 128bit cross lane operations in AVX512 give better performance?

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