How to know if a register is a “general purpose register”?

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The term General purpose register(GPR) stands in contrast to Special purpose Register. The latter cannot be used in all contexts.

Historically the old 8086 architecture introduced this difference for integer registers present in their names till today:

  • AX = Accumulator register: accumulates the result(**)
  • BX = Base register: base offset for certain instruction, e.g. XLAT
  • CX = Counter register: counts for loops, e.g. JCXZ.
  • DX = Data register: extends the data range, e.g. the result of MUL is in DX:AX
  • SI = Source index: source for string instructions, e.g. LODSB
  • DI = Destination index: destination for string instructions, e.g. STOSB
  • SP = Stack pointer: points to the current item of the stack
  • BP = Base pointer: points to the base of the current subroutine (stack frame)

(**) AX/AL is some kind of special purpose register, too. Many instructions have special encodings for AX/AL as operands, e.g. loading segment registers with MOV.

Other Special Purpose Registers were

  • Segment registers (CS,DS,ES,SS)
  • Flags register (FLAGS) and
  • Instruction Pointer (IP)

Some of these restrictions are used till today in the addressing mode for 16-bit instructions in real-mode (See Intel® 64 and IA-32 Architectures
Software Developer’s Manual Volume 2, Section 2.1.5, Table 2-1. “16-Bit Addressing Forms with the ModR/M Byte”)

With the introduction of the 32-bit architecture – IA-32 – the purpose of the integer registers generalized and (nearly) each register can be used for every purpose (hence general purpose). This also reflects in the addressing mode encoding of the instructions, see Intel Manual Volume 2, Section 2.1.5, Table 2.2. (Compare Table 2.1 with Table 2.2 to get an idea of the difference)

The names got prefixed with an E and an R to EAX and RAX, respectively, and their historic names indicating the usage are now merely conventional.

With many new architectures new special purpose registers were added. A complete overview is given in the Intel Manual, Volume 1, Section 3.7.2.:

  • 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP)
  • 16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP)
  • 8-bit general-purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL)
  • segment registers (CS, DS, SS, ES, FS, and GS)
  • EFLAGS register
  • x87 FPU registers (ST0 through ST7, status word, control word, tag word, data operand pointer, and instruction
    pointer)
  • MMX registers (MM0 through MM7)
  • XMM registers (XMM0 through XMM7) and the MXCSR register
  • control registers (CR0, CR2, CR3, and CR4) and system table pointer registers (GDTR, LDTR, IDTR, and task
    register)
  • debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)
  • MSR registers

A general purpose register is one that can be used for more than one purpose. These purposes are

  • value
  • addressing
  • indexing
  • (counting)
  • (base)

A segment register, for example, can only hold a segment value but cannot be used in an addition. And a FPU register can only hold a floating points value but cannot be used for addressing.

In IA-32 the ESP register is closer to being a general purpose register because it can be used for (nearly) all of the above purposes:

  • as value: mov eax, esp
  • in addressing: mov eax, [esp+4], but not as (scaled) index like mov eax, [4+esp*2]
  • as base: mov eax, [esp + eax]
  • as count: inc esp before a jump is valid

The only exception for ESP is that the (scaled) index addressing cannot be encoded. It can only be used as a base register which is exceptionally encoded with a SIB-byte (see Intel Manual, Volume 2, Section 2.1.5, Table 2.3 – see footer).

To illustrate the difference in encoding between ESP and the other registers (e.g. ECX):

8b 01         mov eax, [ecx]   ; MOV + ModRM (normal)
8b 04 24      mov eax, [esp]   ; MOV + ModRM + SIB byte
8b 41 04      mov eax, [ecx+4] ; MOV + ModRM + disp8
8b 44 24 04   mov eax, [esp+4] ; MOV + ModRM + SIB + disp8

I guess despite this one exception ESP can still count itself a GPR.

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